1. Field of the Invention
The present invention relates to semiconductor devices; and, more particularly, to a semiconductor device employing a dielectric layer and a method for fabricating the same.
2. Description of Related Art
In general, as the trend of semiconductor devices goes to high integration, miniaturization and high-speed operation, the area assigned to the capacitor is also being reduced. However, despite of the trend of the semiconductor device, the capacitor should attain a minimum capacitance capable of driving the semiconductor device.
As one solution of securing the minimum capacitance, the bottom electrode of the capacitor is fabricated in various structural configurations, such as a cylinder, a stack, a pin and including concave structures, thereby maximizing the effective surface area of the bottom electrode of the capacitor in a limited and reduced area.
As another solution of securing the minimum capacitance, there is provided as the dielectric layer of the capacitor, dielectric layers having a high dielectric constant such as BST and Ta2O5, and ferroelectrics layers such as SBTN((Sr, Bi)(Ta, Nb)2O9), SBT((Sr, Bi)Ta2O9) and BLT((Bi, La)Ti3O12). In case of employing a dielectric layer having a high dielectric constant and a ferroelectrics layer, with respect to electric properties, the top and the bottom electrode of the capacitor are formed by using metals such as Pt, Ir, Ru, IrO, RuO, Pt-alloy, TiN and so on.
In particular, when forming the bottom electrode of the capacitor by using the above metals, there is employed a poly-Si plug (PP) structure in which a storage node contact plug is formed on a semiconductor substrate for providing the connection with a transistor, which includes a word line and a bit line and was already fabricated on the semiconductor substrate, and then, the bottom electrode is connected to the storage node contact plug.
Referring to FIGS. 1A and 1B, there are shown cross-sectional views showing process steps of a conventional method for fabricating a semiconductor device.
As illustrated in FIG. 1A, a gate oxide film 12 and a word line 13 are formed on a semiconductor substrate 11.
Then, a source electrode 14a and a drain electrode 14b are formed at both sides of the word line 13 by implanting impurity ions into the substrate 11. A first interlayer insulating layer 15 is made on the overall surface of an intermediate product including the substrate 11.
After forming a first contact hole exposing the surface of the drain electrode 14b (or the source electrode 14a) by selectively etching the first interlayer insulating layer 15, tungsten is deposited on the surface of the first interlayer insulating layer 15 and the first contact hole.
Subsequently, there is made a bit line contact (BLC), i.e., a tungsten plug 16, which is filled in the first contact hole through the use of an etch-back or a chemical mechanical polishing (CMP) method.
Next, a bit line 17 is formed connected to the drain electrode 14b through the tungsten plug 16 by depositing a conductive layer for the bit line on the first interlayer insulating layer 15 and the tungsten plug 16 and selectively patterning the deposited conductive layer.
A second interlayer insulating layer 18 is deposited on the overall surface of the intermediate product including the bit line 17 and planarized. Next, a second contact hole is formed by exposing the surface of the source 14a (or drain electrode 14b) by sequentially etching the second and the first interlayer insulating layers 18 and 15 through the use of a patternized photoresist film as a mask (not shown). The second contact hole is generally called a storage node contact hole.
Then, a poly-Si plug 19 is formed and recessed in the inside of the second contact hole by depositing poly-Si on the second interlayer insulating layer 18 and the second contact hole and performing an etch-back or a CMP for the deposited poly-Si.
A titanium(Ti)-silicide layer 20 is formed on the poly-Si plug 19 by depositing titanium on the second interlayer insulating layer 18 and the poly-Si plug 19 and then performing a rapid thermal process (RTP) on the deposited titanium to thereby cause a reaction between silicon (Si) atoms and the titanium.
The Ti-silicide layer 20 makes ohmic contact between the poly-Si plug 19 and a bottom electrode of a capacitor to be formed later.
After removing unreacted titanium, a titanium-nitride (TiN) layer 21 fills up the remaining portion of the second contact hole by depositing TiN on the second interlayer insulating layer 18 and the Ti-silicide layer 20 and etching the deposited TiN through the use of CMP or etch-back until the surface of the second interlayer insulating layer 18 is exposed.
The TiN layer 21 is used as a barrier metal precluding the inter-diffusion between the poly-Si plug 19 and the bottom electrode.
Next, a glue layer 22 is applied to the second interlayer insulating layer 18 and the TiN layer 21 and then selectively etched to form a third contact hole exposing the surface of the TiN layer 21.
Herein, since the glue layer 22 is nonconductive, the third contact hole is made to electrically connect the bottom electrode including a diffusion barrier layer with the TiN layer 21 and the width of the third contact hole can be wider than that of the second contact hole.
The glue layer 22 is formed for increasing the adhesive force between the bottom electrode and the second interlayer insulating layer 18 and employs IrO2.
As shown in FIG. 1B, a capacitor structure is constructed by sequentially forming a diffusion barrier layer 23, a bottom electrode 24, a dielectric layer 25 and a top electrode 26 on the surface of the glue layer 22 and the third contact hole and by first patterning the top electrode 26 and then the rest of layers, i.e., the dielectric layer 25, the bottom electrode 24 and the diffusion barrier layer 23, and the glue layer 22.
In the conventional capacitor over bit line (COB) structure described above, the process of forming the storage node contact (SNC) consisting of the silicon plug, the Ti-silicide layer and the TiN layer is very important.
The storage node contact should have thermal endurance for a high temperature thermal treatment necessary for the crystallization of the dielectric layer in constructing the capacitor.
When forming the dielectric layer through the use of a metal organic deposition (MOD) method or a Sol-gel method, the underlying layers of the capacitor should have an excellent flatness and it is necessary to form the glue layer positioned between the diffusion barrier layer and the plug. The thinner the glue layer, the better. The reason is that the non-planarized topology, caused in forming the third contact hole made in the nonconductive glue layer so as to connect the diffusion barrier layer and the TiN layer, has a bad effect on the deposition of a following ferroelectric layer.
When forming the contact hole of the glue layer connecting the diffusion barrier layer and the TiN layer, the influence of the non-planarized topology in depositing the dielectric layer should be removed by attaining a high etch selectivity between the interlayer insulating layer and the TiN layer and between the interlayer insulating layer and the glue layer.
In the conventional fabricating method shown in FIGS. 1A and 1B, since the glue layer positioned between the diffusion barrier layer (IrOx/Ir) and the barrier metal layer (TiN/TiSi) is made of IrO2, the glue layer can obtain its essential adhesive property. However, since IrO2 is not a reactive material, the etching of IrO2 is performed through the use of a physical etching method. As a result, a trench xe2x80x9cAxe2x80x9d may be generated as shown in FIG. 2 because the etch selectivity between the interlayer insulating layer and the barrier metal layer is low in the over-etching required for forming the contact hole in the glue layer.
The over-etching makes the non-planarized topology when depositing the dielectric layer constructing the capacitor and. Thus, it is impossible to form a dielectric layer having a uniform thickness, so that there may occur a crack in the dielectric layer in a subsequent thermal treatment. Although a crack may not occur, it is still difficult patterning a capacitor having a non-uniform thickness.
Further, by the non-planarized topology, contact errors can be caused in the storage node contact in the subsequent thermal treatment necessary for the dielectric layer and it is difficult to implement a uniform and reliable semiconductor device since there is a difficulty in controlling the charge flowing from the dielectric layer due to the reduction of the practical contact area between the dielectric layer and the bottom electrode.
The above defects can be caused in capacitors of all semiconductor devices employing a dielectric layer requiring thermal treatment as well as the ferroelectric layer.
It is, therefore, a primary object of the present invention to provide a semiconductor device capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing the oxidative endurance and a process margin. The present invention is also concerned with a method for fabricating the semiconductor device.
In accordance with the present invention, there is provided a semiconductor device comprising: a conductive layer; an insulating layer formed on the conductive layer; a glue layer formed on the insulating layer; a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer; and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.
To produce the inventive semiconductor device, in accordance with one embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming an insulating layer on a first conductive layer; forming a first connection layer which is in contact with the first conductive layer through the insulating layer; forming a glue layer on the insulating layer and the first connection layer; forming an opening which exposes the first connection layer by removing a part of the glue layer; forming a second connection layer, which fills the opening and whose surface is planarized with that of the glue layer; and forming a capacitor including a first electrode formed on the second connection layer and the glue layer, a dielectric layer and a second electrode.
In accordance with another embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming an interlayer insulating layer on a semiconductor substrate where a transistor is formed; forming a contact hole exposing a certain part of the semiconductor substrate by selectively etching the interlayer insulating layer; forming a plug containing silicon, which remains on the interlayer insulating layer in a predetermined thickness and fills up the contact hole; forming a glue layer containing silicon and iridium on the plug and the interlayer insulating layer; forming an opening to expose the plug by selectively etching the glue layer; forming a barrier layer on the glue layer and the opening; planarizing the barrier layer until the surface of the glue layer is exposed; and forming a capacitor including a bottom electrode, a dielectric layer and a top electrode on the barrier layer and the glue layer.
In accordance with still another embodiment of the present invention, there is provided a method for fabricating a semiconductor device, comprising the steps of: stacking an insulating layer and a glue layer on a conductive layer; forming a contact hole exposing a certain surface of the conductive layer by selectively etching the glue layer and the insulating layer; forming a connection unit whose surface is planarized with that of the glue layer by filling up the inside of the contact hole; and forming a capacitor on the connection unit.